Spectrum Challenges and Opportunities for 6G and Navigation (December 3, 2020)

Workshop Topic:  As wireless progresses to 6G, key hardware challenges arise in semiconductors and circuits, arrays, and digital signal processing. This workshop will aim to address the semiconductor/circuit/array challenges and chart a potential course for 6G. For example, with semiconductors and circuits, CMOS output power is low above 75GHz, and CMOS gain is low above 150GHz. The limited performance of CMOS can be addressed in circuit design (massive arrays, low-power, low-resolution architectures) or by pairing CMOS with high-performance SiGe and III-V technologies. High-frequency 6G transceivers need arrays with many very-closely-spaced elements. Such arrays bring critical challenges in high-frequency connections, in fitting the necessary circuits into the small available space, in removing the heat, and in providing many electrical connections into the very small areas. This workshop will address possible research, infrastructure needs, and community concerns regarding the advancement and implementation of 6G technologies.

Workshop Goals:  This workshop will identify research and manufacturing challenges in building 6G devices, circuits and systems and attempt to answer important questions such as a) should future 6G wireless systems abandon the “VLSI-CMOS for everything strategy” and embrace application-specific wireless IC technologies (i.e. semiconductor process technologies optimized specifically for various wireless sub-systems)? b) What are the system, array, and IC design choices across different semiconductor platforms, and what are the trade-offs between system architecture, systems performance, and the potential for high-volume, low-cost manufacturing? and c) To the extent that VLSI-optimized CMOS offers the lowest semiconductor costs, how can effective 6G RF systems be designed using a semiconductor technology that is increasingly marginal to the steadily-increasing carrier frequencies?